Statistical Analysis and Optimization for VLSI: Timing and Power [Paperback]

Covers the statistical analysis and optimization issues arising due to increased process variations in current technologies.

Comprises a valuable reference for statistical analysis and optimization techniques in current and future VLSI design for CAD-Tool developers and for researchers interested in starting work in this very active area of research.

Written by author who lead much research in this area who provide novel ideas and approaches to handle the addressed issues

Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest research in statistical timing and power analysis techniques is included, along with efforts to incorporate parametric yield as the key objective function during the design process. Included is the necessary mathematical background on techniques which find widespread use in current analysis and optimization. The emphasis is on algorithms, modeling approaches for process variability, and statistical techniques that are the cornerstone of the probabilistic CAD movement. The authors also describe recent optimization approaches to timing yield and contrast them to deterministic optimization. The work will enable new researchers in this area to come up to speed quickly, as well as provide a handy reference for those already working in CAD tool development.

Ashish Srivastava received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur in 2001 and the M.S. degree in electrical engineering from the University of Michigan, Ann Arbor in 2003. He is currently pursuing the Ph.D. degree at the University of Michigan, Ann Arbor. In summe r 2003 he was wil3;