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Semiconductor Memories Technology, Testing, and Reliability [Hardcover]

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  • Category: Books (Technology & Engineering)
  • Author:  Sharma, Ashok K.
  • Author:  Sharma, Ashok K.
  • ISBN-10:  0780310004
  • ISBN-10:  0780310004
  • ISBN-13:  9780780310001
  • ISBN-13:  9780780310001
  • Publisher:  Wiley-IEEE Press
  • Publisher:  Wiley-IEEE Press
  • Pages:  480
  • Pages:  480
  • Binding:  Hardcover
  • Binding:  Hardcover
  • Pub Date:  01-May-2002
  • Pub Date:  01-May-2002
  • SKU:  0780310004-11-MPOD
  • SKU:  0780310004-11-MPOD
  • Item ID: 100881662
  • List Price: $222.50
  • Seller: ShopSpell
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  • Delivery by: Apr 09 to Apr 11
  • Notes: Brand New Book. Order Now.
Semiconductor Memories provides in-depth coverage in the areas of design for testing, fault tolerance, failure modes and mechanisms, and screening and qualification methods including.
* Memory cell structures and fabrication technologies.
* Application-specific memories and architectures.
* Memory design, fault modeling and test algorithms, limitations, and trade-offs.
* Space environment, radiation hardening process and design techniques, and radiation testing.
* Memory stacks and multichip modules for gigabyte storage.Preface.

Chapter 1: Introduction.

Chapter 2: Random Access Memory Technologies.

2.1 Introduction.

2.2 Static Random Access Memories (SRAMs).

2.3 Dynamic Random Access Memories (DRAMs).

Chapter 3: Nonvolatile Memories.

3.1 Introduction.

3.2 Masked Read-Only Memories (ROMs).

3.3 Programmable Read-Only Memories (PROMs).

3.4 Erasable (UV)-Programmable Read-Only Memories (EPROMs).

3.5 Electrically Erasable PROMs (EEPROMs).

3.6 Flash Memories (EPROMs or EEPROMs).

Chapter 4: Memory Fault Modeling and Testing.

4.1 Introduction . . . .

4.2 RAM Fault Modeling.

4.3 RAM Electrical Testing.

4.4 RAM Pseudorandom Testing.

4.5 Megabit DRAM Testing.

4.6 Nonvolatile Memory Modeling and Testing.

4.7 IDDQ Fault Modeling and Testing.

4.8 Application Specific Memory Testing.

Chapter 5: Memory Design for Testability and Fault Tolerance.

5.1 General Design for Testability Techniques.l3Q

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